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| data sheet mos integrated circuit m pd17p207 4-bit single-chip microcontroller with lcd controller/driver and a/d converter for infrared remote control transmitter description m pd17p207 is a variation of m pd17207 and is equipped with a one-time prom instead of an internal mask rom. m pd17p207 is suitable for evaluating program when developing a m pd17201a and 17207 systems because program can be written by the user. when reading this document, also refer to the m pd17201a, 17207 documents. ordering information part number package m pd17p207gf-001-3b9 80-pin plastic qfp (14 20 mm) m pd17p207gf-002-3b9 80-pin plastic qfp (14 20 mm) m pd17p207gf-003-3b9 80-pin plastic qfp (14 20 mm) the features of each product is shown in the following table: when using m pd17p207-001, be sure to connect the resonator to the main clock oscllator circuit and subclock oscillator circuit. features ? 17k architecture: general-purpose register format ? pin-compatible with m pd17201a, 17207 except prom programming functiom ? internal one-time prom: 4096 16 bits ? supply voltage: 2.5 to 5.5 v (at f x = 4 mhz, t a = C20 to +75 c) 2.4 to 5.5 v (at f x = 4 mhz, t a = C20 to +60 c) 2.0 to 5.5 v (at f xt = 32.768 khz, t a = C20 to +75 c) m pd17p207-001 provided item pull-up resistor of reset pin main clock oscillator circuit subclock oscillator circuit m pd17p207-002 not provided provided not provided m pd17201a, 17207 on request (mask option) m pd17p207-003 not provided provided m pd17p207 is different from m pd17201a, 17207 in some of the electrical characteristics, such as supply voltage, the operating ambient temperature, and supply current. therefore, use m pd17p207 only for the system evaluation. the information in this document is subject to change without notice. the mark shows major revised points. document no. u11777ej3v0ds00 (3rd edition) previous no. ic-2707a date published november 1996 p printed in japan 1993
m pd17p207 2 pin configuration (top view) (1) ordinary operation mode lcd 32 lcd 31 lcd 30 lcd 29 lcd 28 lcd 27 lcd 26 lcd 25 lcd 24 lcd 23 lcd 22 lcd 21 lcd 20 lcd 19 lcd 18 lcd 17 lcd 16 lcd 15 lcd 14 lcd 13 lcd 12 lcd 11 lcd 10 lcd 9 x out x in v dd rem p1a 2 /si p1a 1 /so p1a 0 /sck p0d 3 p0d 2 p0d 1 /tmout p0d o /led p0c 3 p0c 2 p0c 1 p0c 0 p0b 3 p0b 2 p0b 1 p0b 0 p0a 3 p0a 2 p0a 1 p0a 0 int lcd 33 lcd 34 /com 3 lcd 35 /com 2 com 1 com 0 capl caph v lcd2 v lcd1 v lcdc v lcd0 xt out xt in wdout v reg reset lcd 8 lcd 7 lcd 6 lcd 5 lcd 4 lcd 3 lcd 2 lcd 1 gnd lcd 0 v adc adc 0 adc 1 adc 2 adc 3 gnd adc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pd17p207gf-3b9 m m pd17p207 3 (2) prom programming mode caution: those enclosed in parentheses indicate the processing of the pins not used in prom programming mode. l : ground these pins through a resistor (470 w ). open : do not connect anything to these pins. gnd v dd gnd adc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pd17p207gf-3b9 m (open) (open) (open) (l) (open) (l) (open) (l) (open) clk v (open) (l) d d d d md md md md d d d d v 7 6 5 4 3 2 1 0 3 2 1 0 pp dd m pd17p207 4 pin name adc 0 -adc 3 : a/d converter input caph, capl : booster capacitor connection clk : prom clock input com 0 -com 3 : lcd common signal output d 0 -d 7 : prom data i/o gnd, gnd adc : ground int : external interrupt request signal input lcd 0 -lcd 35 : lcd segment signal output led : remote controller transfer display output md 0 -md 3 : prom mode selection input p0a 0 -p0a 3 : i/o port p0b 0 -p0b 3 : i/o port p0c 0 -p0c 3 : i/o port p0d 0 -p0d 3 : i/o port rem : remote controller transfer output reset : reset signal input sck : serial clock i/o si : serial data input so : serial data output tmout : timer output v adc : a/d converter power supply v dd : power supply v lcd0 -v lcd2 : lcd drive voltage output v lcdc : lcd drive reference voltage adjustment v pp : prom writing power supply v reg : voltage regulator output wdout : overrun detection output x in , x out : main clock oscillator circuit xt in , xt out : subclock oscillator circuit m pd17p207 5 block diagram remark inside the parenthesis indicates pin names in the prom programming mode. p1a 0 sck p1a 1 /so p1a 2 /si p0a 0 (d 0 ) p0d 0 /led p0d 1 /tmout p0d 2 p0d 3 rem p1a p0a p0b p0c p0d timer/ counter ram 336 4 bits system reg. one time prom 4096 16 bits program counter stack 5 12 bits instruction decoder v reg v dd caph capl v lcd0 v lcd1 v lcd2 v lcdc gmd lcd 0 lcd 1 lcd 2 lcd 3 lcd 4 lcd 33 com 3 /lcd 34 com 2 /lcd 35 com 1 com 0 cpu clock clock stop cpu clock v adc adc 0 adc 1 adc 2 adc 3 gnd adc interrupt controller lcd controller reset wdout x out xt in xt out power supply circuit alu watch timer divider main clock subclock rf serial interface p0a 1 (d 1 ) p0a 2 (d 2 ) p0a 3 (d 3 ) p0b 0 (md 0 ) p0b 1 (md 1 ) p0b 2 (md 2 ) p0b 3 (md 3 ) p0c 0 (d 4 ) p0c 1 (d 5 ) p0c 2 (d 6 ) p0c 3 (d 7 ) int (v ) pp a/d converter x (clk) in carrier generator m pd17p207 6 contents 1. pin functions ................................................................................................................ ................. 7 1.1 ordinary operation mode ..................................................................................................... ......... 7 1.2 prom programming mode ....................................................................................................... ......... 9 1.3 equivalent circuits of pins ................................................................................................. ........ 10 1.4 processing of unused pins ................................................................................................... ....... 11 1.5 notes on using reset and int pins (only in ordinary operation mode) ................... 12 2. one-time prom (program memory) writing, reading, and verification ............... 13 2.1 operation mode for writing, reading, and verification of program memory ..... 13 2.2 program memory write procedure ......................................................................................... 14 2.3 program memory read procedure ........................................................................................... 15 3. defferences between m pd17p207 and m pd17201a/17207 ................................................. 16 4. electrical characteristics ................................................................................................. 17 5. package drawings ............................................................................................................. ........ 25 6. recommended soldering conditions ................................................................................ 26 appendix a. microcontroller family for high-function remote controller with lcd ....................................................................................................................... . 27 appendix b. development tools ................................................................................................ 28 m pd17p207 7 1. pin functions 1.1 ordinary operation mode pin no. symbol function output type on reset 76 com 0 77 com 1 78 lcd 35 /com 2 79 lcd 34 /com 3 cmos, 80 lcd 33 push-pull 1 lcd 32 || 32 lcd 1 34 lcd 0 33 gnd CC 35 v adc CC 36 adc 0 || CC 39 adc 3 40 gnd adc CC C input 41 int 42 p0a 0 cmos, || push-pull input 45 p0a 3 46 p0b 0 n-channel, || open-drain input 49 p0b 3 50 p0c 0 n-channel, || open-drain input 53 p0c 3 54 p0d 0 /led 55 p0d 1 /tmout cmos, input 56 p0d 2 push-pull 57 p0d 3 common/segment signal outputs of the lcd driver. these common and segment signal outputs are selected by lcdmd3 to lcdmd0 of the register file. ? com 0 to com 3 common signal outputs of the lcd driver ? lcd 35 to lcd 0 segment signal outputs of the lcd driver device ground positive power supply of the a/d converter (v adc should be equal to v dd .) analog inputs of the a/d converter (8-bit resolution) ground of the a/d converter external interrupt request signal (input). the interrupt request is generated at the rising edge of this signal. 4-bit i/o port (enabling setting of inputs or outputs in 4-bit units) (grouped i/o). each of these pins has a pull-up resistor. 4-bit i/o port (enabling setting of inputs or outputs in 4-bit units) (grouped i/o). 4-bit i/o port (enabling setting of inputs or outputs in 4-bit units) (grouped i/o). port 0d/led output or 8-bit timer output. p0d 0 and led outputs are switched by nrzen of the register file. p0d 1 and 8-bit timer outputs are switched by tmoe of the register file. ? p0d 0 to p0d 3 4-bit i/o port enabling setting of inputs or outputs of each bit (bitwise i/o) ? led outputs nrz signal in synchronization with infrared remote controller signal (rem) outputs high level while remote controller carrier is output from rem pin ? tmout output of the 8-bit timer (to be contd) C m pd17p207 8 (contd) pin no. symbol function output type on reset port 1a or serial interface. port 1a and serial interface are switched by sioen of the register file. 58 p1a 0 /sck ? p1a 0 to p1a 2 3-bit i/o port cmos, input 59 p1a 1 /so enabling setting of inputs or outputs of 3 bits push-pull (grouped i/o) 60 p1a 2 /si ? sck, so, si sck: serial clock i/o so: serial data output si: serial data input 61 rem signal output to an infrared remote controller. cmos, low-level active-high output push-pull output 62 v dd positive power supply. C C 63 x in these pins are connected to a 4-mhz ceramic or crystal 64 x out resonator for main clock oscillation. system reset input 65 reset system is reset when low level is input to this pin. C input while this pin is low, oscillation of main clock is stopped. only m pd17p207-001 has internal pull-up resistor. output of the voltage regulator for the subclock oscillation 66 v reg circuit. C C connect external 0.1- m f capacitor to this pin. output for detection of a program overrun. n-channel, high- 67 wdout outputs low level when the watchdog timer overflows or the open drain impedance stack overflows/underflows. use this pin after connecting to the reset pin. 68 xt in these pins are connected to a 32.768-khz crystal oscillator C (oscillates.) 69 xt out for subclock oscillation. 71 v lcdc input to regulate the reference voltage to drive lcd. C C 70 v lcd0 reference voltage outputs to drive lcd. 72 v lcd1 ?v lcd0 : reference voltage output 73 v lcd2 ?v lcd1 : doubler output (two times the reference voltage) C C ?v lcd2 : tripler output (three times the reference voltage) 74 caph these pins are connected to a capacitor to boost the CC 75 capl lcd drive voltage. (oscillation stops.) m pd17p207 9 40 gnd adc CC 33 gnd ground C C 35 v dd positive power supply C C ground for a/d converter performs prom programming with gnd adc = gnd. positive power supply for prom programming. 41 v pp applies 12.5v as the program voltage when writing, reading, C C and verifying the program memory. 42 d 0 to to 45 d 3 50 d 4 to to 53 d 7 46 md 0 to to select operation mode for prom programming. C input 49 md 3 62 v dd positive power supply C C 63 clk address update clock input C input remark pins other than the above are not used in the prom programming mode. for the processing of unused pins, refer to (2) prom programming mode in pin configuration . 1.2 prom programming mode pin no. symbol function output type on reset 8-bit data i/o for prom programming. input cmos, push-pull m pd17p207 10 1.3 equivalent circuits of pins the followings are equivalent circuits (partially simplified) of the respective pins of the m pd17p207. (1) p0a (4) p0d, p1a note only m pd17p207-001 has the internal pull-up resistor. (3) p0c (6) int (2) p0b (5) reset v dd v dd output latch p-ch n-ch data output disable selector input buffer v dd output latch p-ch n-ch data output disable selector input buffer output latch n-ch data output disable input buffer input buffer pull-up resistor note v dd input buffer output latch n-ch data output disable selector input buffer schmitt trigger input with hysteresis characteristics schmitt trigger input with hysteresis characteristics m pd17p207 11 1.4 processing of unused pins in ordinay operation mode, process unused pins as follows: table 1-1. processing of unused pins (a) port pins recommended processing of unused pins pin name internally externally input mode p0a (connect pull-up resistor.) open p0c C directly connect to gnd. p0d, p1a C connect each pin to v dd or gnd via resistor note . output mode p0a (cmos port) outputs high level open p0d, p1a (cmos port) C p0b, p0c (n-ch open-drain port) outputs low level note when externally pulling a pin up (connecting the pin to v dd via resistor) and down (connecting the pin to gnd via resistor), give adequate consideration to the drive capability and current consumption of the port. to pull a pin up or down at a high resistance, make sure that no noise is superimposed on the pin. (b) pins other than port pins pn name i/o mode recommended processing of unused pin adc 0 -adc 3 input directly connect to gnd caph, capl output open com 0 , com 1 , com 2 /lcd 35 , com 3 /lcd 34 output open int note input directly connect to gnd lcd 0 -lcd 33 output open rem output open v adc C directly connect to v dd v lcd0 -v lcd2 output open v lcdc C directly connect to v dd or v lcd0 wdout output directly connect to gnd x in , xt in input directly connect to gnd x out C directly connect to v dd xt out C directly connect to v reg note the int pin is also used as a test mode setting pin. directly connect this pin to gnd when it is not used. cautions 1. it is recommended that the input/output mode and output level of a pin be fixed by repeatedly setting in each loop of the program. 2. when the lcd controller/driver is not used, stop the voltage regulator by using the display mode register. m pd17p207 12 1.5 notes on using reset and int pins (only in ordinary operation mode) in addition to the functions shown in 1. pin functions, the reset and int pins also have a function to set a test mode (for ic testing) in which the internal operations of the m pd17p207are tested. when a voltage higher than v dd is applied to either of these pins, the test mode is set. this means that, even during ordinary operation, the m pd17p207 may be set in the test mode if a noise exceeding v dd is applied. for example, if the wiring length of the reset or int pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. ? connect diode with low v f between v dd and reset/int pin ? connect capacitor between v dd and reset/int pin v dd v dd v dd v dd reset, int diode with low v f reset, int m pd17p207 13 2. one-time prom (program memory) writing, reading, and verification m pd17p207 sets the prom mode when prom writing, reading or verification as shown in table 2-1. in prom mode, no address input pin is used. instead, the address is updated by the clock for input from the clk pin. function applies program voltage (12.5 v). inputs address update clock. selects operation mode. inputs and outputs 8-bit data. applies supply voltage (6 v). pin name v pp clk md 0 -md 3 d 0 -d 7 v dd 2.1 operation mode for writing, reading, and verification of program memory if +6 v is applied to the v dd and +12.5 v to the v pp pin after m pd17p207 has been placed in the reset status for a fixed time (v dd = 5v, reset = low level), m pd17p207 enters program memory write, read, or verify mode. the md 0 to md 3 pins are used to set the operation modes listed in table 2-2. leave the pins not used for program memory writing, reading, or verification open or ground through pull-down resistors (470 w ). (refer to (2) prom programming mode in pin configuration .) table 2-2. operating mode for program memory writing, reading or verification operating mode specification remark x: l or h md 0 md 1 md 2 md 3 hlhl lhhh llhh hxhh v dd +6 v v pp +12.5 v operating mode program memory address 0 clear mode write mode read/verify mode program inhibit mode table 2-1. pins used for program memory writing, reading, or verification m pd17p207 14 2.2 program memory write procedure the program memory write procedure is as follows. high-speed program memory write is possible. (1) ground the unused pins through pull-down resistors. the clk pin must be low. (2) supply 5 v to the v dd pin. the v pp pin must be low. (3) after waiting for 10 m s, supply 5 v to the v pp pin. (4) operate the md0 to md3 pins to set program memory address 0 clear mode. (5) supply 6 v to the v dd pin and 12.5 v to the v pp pin. (6) set program inhibit mode. (7) write data in 1-millisecond write mode. (8) set program inhibit mode. (9) set verify mode. if data has been written connectly, proceed to step (10). if data has not yet been written, repeat steps (7) to (9). (10) write additional data for (the number of times data was written (x) in steps (7) to (9)) times 1 milliseconds. (11) set program inhibit mode. (12) supply a pulse to the clk pin four times to update the program memory address by 1. (13) repeat steps (7) to (12) to the last address. (14) set program memory address 0 clear mode. (15) change the voltages of v dd and v pp pins to 5 v. (16) turn off the power supply. steps (2) to (12) are illustrated below. reset v pp v dd gnd v dd +1 v dd gnd v pp v dd data input data output data input write verify additional data write address increment x-time repetition d -d 0 7 md 0 md 1 md 2 md 3 clk hi-z hi-z hi-z hi-z m pd17p207 15 2.3 program memory read procedure (1) ground the unused pins through pull-down resistors. the clk pin must be low. (2) supply 5 v to the v dd pin. the v pp pin must be low. (3) after waiting for 10 m s, supply 5 v to the v pp pin. (4) operate the md0 to md3 pins to set program memory address 0 clear mode. (5) supply 6 v to the v dd pin and 12.5 v to the v pp pin. (6) set program inhibit mode. (7) set verify mode. data of each address is sequentially output each time a clock pulse is input to the clk pin four times. (8) set program inhibit mode. (9) set program memory address 0 clear mode. (10) change the voltages of v dd and v pp pins to 5 v. (11) turn off the power supply. steps (2) to (9) are illustrated below. v pp v dd gnd v dd +1 v dd gnd clk v pp v dd data output data output l 1 cycle d -d 0 7 md 0 md 1 md 2 md 3 reset hi-z hi-z m pd17p207 16 3. differences between m pd17p207 and m pd17201a/17207 the m pd17p207 has a prom to which the user can write a program in place of the internal mask rom (program memory) of the m pd17201a and 17207. therefore, the m pd17p207 is identical to m pd17201a and 17207 except for the program memory and mask option. however, some of the electrical characteristics, such as supply current or v lcdc voltage of the m pd17p207, are different from that of the m pd17201a and 17207. the following table lists the differences between the m pd17p207 and m pd17201a/17207. for the details of the cpu and hardware of the m pd17201a and 17207, refer to their data sheets. item m pd17p207 m pd17p207 m pd17p207 m pd17201a m pd17207 product name -001 -002 -003 program memory one-time prom mask rom 0000h-0fffh 0000h-0bffh 0000h-0fffh 4096 16 bits 3072 16 bits 4096 16 bits pull-up resistor of reset pin not provided not any main clock oscillator circuit provided provided provided (mask option) subclock oscillator circuit not provided provided v pp pin, prom programming pin provided not provided supply voltage v dd = 2.5 to 5.5 v (at f x = 4 mhz, t a = C20 to +75 c) v dd = 2.2 to 5.5 v (at f x = 4 mhz) (t a = C20 to +75 c) v dd = 2.4 to 5.5 v (at f x = 4 mhz, t a = C20 to +60 c) package 80-pin plastic qfp (14 20 mm) m pd17p207 17 4. electrical characteristics absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd C0.3 to +7.0 v analog supply voltage v adc C0.3 to +7.0 v input voltage vi C0.3 to v dd +0.3 v output voltage v o C0.3 to v dd +0.3 v peak value C30 ma rem pin rms value C20 ma high-level one pin peak value C7.5 ma output current i oh (except rem) rms value C5 ma all pins peak value C22.5 ma (except rem) rms value C15 ma peak value 7.5 ma one pin low-level rms value 5 ma output current i ol all pins peak value 22.5 ma (except rem) rms value 15 ma operating ambient temperature t a C20 to +75 c storage temperature t stg C40 to +125 c note rms value = peak value duty caution even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. the absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. be sure not to exceed or fall below this value when using the product. capacitance (t a = 25 c, v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c in1 int and reset pins 10 pf c in2 other than int and reset pins 10 pf recommended operating ranges (t a = C20 to + 75 c) parameter symbol conditions min. typ. max. unit system clock f x = 4 mhz 2.5 3.0 5.5 v f x = 4 mhz, t a = C20 to + 60 c 2.4 3.0 5.5 v v dd2 system clock f x = 8 mhz 4.5 5.0 5.5 v v dd3 system clock f xt = 32.768 khz 2.0 3.0 5.5 v main clock oscillation frequency f x 1.0 4.0 8.0 mhz subclock oscillation frequency f xt 32.768 khz v dd1 supply voltage m pd17p207 18 main system clock oscillator characteristics (t a = C20 to +75 c, v dd = 2.5 to 5.5 v) recommended constants oscillation 1.0 4 8.0 mhz frequency (f x ) note 1 from when v dd oscillation note 2 reaches the 4 ms stabilization time minimum oscillation voltage 1.0 4 8.0 mhz v dd = 4.5 to 5.5v 10 ms 30 ms notes 1. the oscillation frequency is indicated only to express the oscillator characteristics. refer to the ac characteristics for instruction execution time. 2. the oscillation stabilization time is the time required for stabilizing the oscillation after vdd is applied or the stop mode is released. 3. the recommended resonators are shown in the table described later. subsystem clock oscillator characteristics recommended constants 32.768 khz 510s caution when using the main system clock and the subsystem clock generators, in order to avoid wiring capacitance effects, the following notations must be read and observed for wiring the portion inside the dotted line in the table: ? wiring length must be minimized. ? do not cross with other signal lines. do not wire close to a large current line. ? capacitors used in the oscillators must always be grounded to gnd potential level. never ground the grounding pattern having a large current flow. ? do not take the signal directly out of the oscillator. in order to reduce the power consumption, the subsystem clock oscillator employs a low amplifi- cation factor circuit. because of this, the subsystem clock oscillator is more sensitive to noise than the main system clock oscillator. therefore, when using the subsystem clock, wiring must be carefully planned. resonator item conditions min. typ. max. unit oscillation frequency (f x ) note 1 oscillation note 2 stabilization time note 3 ceramic resonator note 3 crystal resonator resonator item conditions min. typ. max. unit crystal resonator oscillation stabilization time oscillation frequency (f xt ) x in x out c2 c1 x in x out c2 c1 x in x out m pd17p207 19 recommended resonators main system clock : ceramic resonator external oscillation capacitance (pf) voltage range (v) manufacturer part name remarks c1 c2 min. max. csa3.58mg 30 30 2.0 6.0 csa4.00mg 30 30 2.0 6.0 csa4.19mg 30 30 2.0 6.0 murata mfg. cst3.58mgw not not 2.0 6.0 required required cst4.00mgw not not 2.0 6.0 built-in capacitor required required cst4.19mgw not not 2.0 6.0 required required kbr3.58ms 33 33 2.0 6.0 kyocera kbr4.0ms 33 33 2.0 6.0 kbr4.19ms 33 33 2.0 6.0 toko crhf4.00 18 18 2.0 6.0 daishinku prs0400bcsan 39 33 2.0 6.0 main system clock : crystal resonator external oscillation manufacturer frequency holder capacitance (pf) voltage range (v) remarks (mhz) c1 c2 min. max. kinseki 4.0 hc-49u-s 22 22 2.0 6.0 m pd17p207 20 dc characteristics (t a = C20 to +75 c, v dd = v adc = 3 v) parameter symbol test condition min. typ. max. unit v ih1 reset and int pins 2.4 3 v high-level input voltage v ih2 other than reset and int pins 2.1 3 v v il1 reset and int pins 0 0.6 v low-level input voltage v il2 other than reset and int pins 0 0.9 v i lih1 xt in , xt out , x in , and x out pins 20 m a i lih2 other than xt in , xt out , x in , and x out pins 3 m a i lil1 xt in , xt out , x in , and x out pins C20 m a i lil2 other than xt in , xt out , x in , and x out pins C3 m a i oh1 rem pin v oh = 1.8 v C7 C15 ma high-level output current i oh2 note 1 v oh = 2.7 v C0.3 C0.7 ma low-level output current i ol note 2 v ol = 0.3 v 0.5 0.9 ma r p0a p0a0 to p0a3 pins 100 200 350 k w built-in pull-up resistor r res reset pins ( m pd17p207-001 only) 24 47 94 k w a/d absolute precision 2 lsb a/d resolution 8 bits a/d converter current i adc 60 120 m a consumption comparator error in comparator mode 10 20 mv i dd1 x installed run mode 1.6 2.2 ma (f x = 4.19 mhz) i dd2 xt not installed halt mode 1.8 ma supply current i dd3 stop mode 3.0 10.0 m a i dd4 x not installed or stop run mode 400 600 m a mode xt installed i dd5 (f xt = 32.768 khz) halt mode 20 40 m a notes 1. p0a 0 to p0a 3 , p0d 0 to p0d 3 , and p1a 0 to p1a 2 pins 2. p0a 0 to p0a 3 , p0b 0 to p0b 3 , p0c 0 to p0c 3 , p0d 0 to p0d 3 , p1a 0 to p1a 2 , wdout, and rem pins 3. the specifications of the main stop mode (sub-mounting) are the same as the sub-halt mode (with the main clock oscillation stopped). lcd characteristics (t a = C20 to +75 c, v dd = 3 v) parameter symbol test condition min. typ. max. unit vlcdc output voltage v lcdc t a = 25 c, r1 = r2 = 1 m w 0.5 0.65 0.8 v lcd reference output voltage v lcd0 external variable resistance 0.8 1.8 v (0 to 2.2 m w ) doubler output voltage v lcd1 c1 to c4 = 0.47 m f 1.9 2.0 v lcd0 tripler output voltage v lcd2 c1 to c4 = 0.47 m f 2.85 3.0 v lcd0 lcd common output current i com output voltage deviation = 0.2 v 30 m a lcd segment output current i lcd output voltage deviation = 0.2 v 5 m a high-level input leakage current low-level input leakage current note 3 m pd17p207 21 ac characteristics (t a = C20 to +75 c, v dd = 2.0 to 5.5 v) parameter symbol condition min. typ. max. unit data input 2.0 m s v dd = 5 v 10 % data output 10 m s sck input cycle time t kcy data input 5 m s data output 13 m s data input 1.0 m s v dd = 5 v 10 % sck input high- and t kh , data output 5.0 m s low-level widths t kl data input 2.5 m s data output 6.5 m s si setup time (vs. sck )t sik 100 ns si hold time (vs. sck )t ksi 100 ns sck ?? to so t kso c l = 100 pf 4.5 m s output delay time int high-and low-level width t ioh , t iol 50 m s reset low-level width t rsl 50 m s p0a low-level width t rlsl at standby release 10 m s serial transfer timing 3-line serial i/o mode: sck si so input data output data t kcy t kl t kh t ksi t sik t kso m pd17p207 22 dc programming characteristics (t a = 25 c, v dd = 6.0 0.25v, v pp = 12.5 0.3v) parameter symbol conditions min. typ. max. unit 0.7 v dd v dd v v dd C0.5 v dd v 0 0.3 v dd v 0 0.4 v 10 m a v dd C1.0 v 0.4 v 30 ma 30 ma other than clk clk other than clk clk v in = v il or v ih i oh = C1 ma i ol = 1.6 ma md 0 = v il , md 1 = v ih v ih1 v ih2 v il1 v il2 i li v oh v ol i dd i pp high-level input voltage low-level input voltage input leakage current high-level output voltage low-level output voltage v dd supply current v pp supply current cautions 1. v pp must not exceed +13.5 v, including the overshoot. 2. apply v dd before v pp and disconnect it after v pp . m pd17p207 23 2 m s 2 m s 2 m s 2 m s 2 m s 0130 m s 2 m s 2 m s 0.95 1.0 1.05 ms 0.95 21.0 ms 2 m s 1 m s 2 m s 2 m s 10 m s 0.125 m s 4 mhz 2 m s 2 m s 2 m s 2 m s 2 m s 0130 m s 2 m s 2 m s 10 m s ac programming characteristics (t a = 25 c, v dd = 6.0 0.25v, v pp = 12.5 0.3v) parameter symbol note 1 conditions min. typ. max. unit notes 1. these symbols are the corresponding m pd27c256a (maintenance product) symbols. 2. the internal address is incremented by 1 at the third falling edge of clk (with four clocks constituting as one cycle). the internal address is not connected to any pin. t as t as t m1s t oes t ds t ds t ah t ah t dh t dh t df t df t vps t vps t vds t vcs t pw t pw t opw t opw t mos t ces t dv t dv t m1h t oeh t m1r t or t pcr C t xh ,t xl C f x C t i C t m3s C t m3h C t m3sr C t dad t acc t had t oh t m3hr C t dfr C t res C md 0 = md 1 = v il t m1h + t m1r 50 m s when data is read from program memory address setup time note 2 (vs.md 0 ? ) md 1 setup time (vs. md 0 ? ) data setup time (vs. md 0 ? ) address hold time note 2 (vs.md 0 ) data hold time (vs. md 0 ) md 0 ? data output float delay time v pp setup time (vs. md 3 ) v dd setup time (vs. md 3 ) initial program pulse width additional program pulse width md 0 setup time (vs. md 1 ) md 0 ?? data output delay time md 1 hold time (vs. md 0 ) md 1 recovery time (vs. md 0 ? ) program counter reset time clk input high-/low- level width clk input frequency initial mode set time md 3 setup time (vs. md 1 ) md 3 hold time (vs. md 1 ? ) md 3 setup time (vs. md 0 ? ) address note 2 ? data output delay time address note 2 ? data output hold time md 3 hold time (vs. md 0 ) md 3 ?? data output float delay time reset setup time m pd17p207 24 program memory write timing program memory read timing v pp v dd gnd v dd +1 v dd gnd clk md 0 md 1 md 2 md 3 v pp v dd data input data output data input data input t res t vps t vds t t ds t dh tt dv t df t ds t ah t as t opw t t m1r t pw t pcr t m1s t m1h t m3s t m3h v pp v dd gnd v dd +1 v dd gnd clk md 0 md 1 md 2 md 3 v pp v dd t res t vps t vds t t dv t xh t xl t had t dad data output data output t dfr t m3hr l t pcr t m3sr t xh t xl d 0 to d 7 d 0 to d 7 i oh mos i hi-z hi-z hi-z hi-z hi-z hi-z hi-z m pd17p207 25 5. package drawings item millimeters inches g q f 1.8 0.125?.075 1.0 s 0.031 0.005?.003 0.039 s80gf-80-3b9-3 note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 3.0 max. 0.119 max. d 17.2?.2 0.677?.008 r5 ? 5 ? b 20.0?.2 0.787 +0.009 ?.008 a 23.2?.2 0.913 +0.009 ?.008 80 pin plastic qfp (14 20) c 14.0?.2 0.551 +0.009 ?.008 j 0.8 (t.p.) 0.031 (t.p.) i 0.15 0.006 h 0.35?.10 0.014 +0.004 ?.005 p 2.7 0.106 n 0.10 0.004 l 0.8?.2 0.031 +0.009 ?.008 m 0.15 0.006 +0.004 ?.003 k 1.6?.2 0.063?.008 +0.10 ?.05 detail of lead end m 64 65 40 80 1 25 24 41 a b c d f g h i j k m l n p s q r m pd17p207 26 6. recommended soldering conditions when mounting the m pd17p207 by soldering, soldering should be performed under the following recommended contitions. for details on recommended soldering conditions, refer to the information document semconductor device mounting technology manual (c10535e). for other soldering methods, please cousult with nec sales personnel. table 6-1. conditions for surface mounting m pd17p207gf-001-3b9 : 80-pin plastic qfp ( 14 20 mm) m pd17p207gf-002-3b9 : 80-pin plastic qfp ( 14 20 mm) m pd17p207gf-003-3b9 : 80-pin plastic qfp ( 14 20 mm) recommended soldering method soldering conditions conditions reference code package peak temperature: 235 c, time: 30 seconds max. (210 c min.), infrared reflow number of times: 2 max., number of days: 7 note (after that, prebaking is ir35-207-2 necessary at 125 c for 20 hours) m pd17p207 27 m pd17201a m pd17207 m pd17p207 instruction execution time item supply voltage (t a = C20 to +75 c) 2 channels appendix a. microcontroller family for high-function remote controller with lcd product name rom capacity 3072 16 bits 4096 16 bits 4096 16 bits (mask rom) (mask rom) (one-time prom) ram capacity 336 4 bits lcd controller/driver 136 segments max. infrared remote controller led output is high-active. carrier generator number of i/o ports 19 external interrupt (int) 1 timer 8-bit timer : 1 watch timer : 1 watchdog timer internal (wdout output) serial interface 1 channel stack 5 levels (3 levels for multiplexed interrupt) main system 4 m s (4 mhz: with ceramic or crystal oscillator) clock subsystem 488 m s (32.768 khz: with crystal osciallator) clock main 2.5 to 5.5 v system 2.2 to 5.5 v clock 2.4 to 5.5 v note subsystem 2.0 to 5.5 v clock standby function stop, halt pakcage 80-pin plastic qfp note t a = C20 to + 60 c m pd17p207 28 appendix b. development tools to develop the programs for the m pd17p207, the following development tools are available: hardware name remarks ie-17k, ie-17k-et, and emu-17k are the in-circuit emulators used in common with the 17k series microcomputer. ie-17k and ie-17k-et are connected to a pc-9800 series or ibm pc/at tm as the host machine with rs-232c. emu-17k is inserted into the expansion slot of a pc-9800 series. by using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. a higher level debugging environment can be provided by using man-machine interface simplehost tm . emu-17k also has a function by which you can check the contents of data memory realtime. se board this is an se board for m pd17201a, 17207, and 17p207. it can be used alone to evaluate (se-17207) a system or in combination with an in-circuit emulator for debugging. emulation probe ep-17201gf is an emulation probe for m pd17201a, 17207, and 17p207. when used with (ep-17201gf) ev-9200g-80, it connects an se board to the target system. conversion socket ev-9200g-80 is a conversion socket for 80-pin qfp (14 20 mm) and is used to connect (ev-9200g-80 note 3 ) ep-17201gf to the target system. prom programmer af-9703, af-9704, af-9705, and af-9706 are prom programmers corresponding to (af-9703 note 4 , m pd17p207. by connecting program adapter af-9808a to this prom programmer, af-9704 note 4 , m pd17p207 can be programmed. af-9705 note 4 , af-9706 note 4 ) program adapter af-9808a is an adapter that is used to program m pd17p207, and is used in combination (af-9808 note 4 ) with af-9703, af-9704, af-9705, or af-9706. notes 1. low-cost model: external power supply type 2. this is a product from ic corp. for details, consult ic corp. 3. two ev-9200g-80s are supplied with the ep-17201gf. five ev-9200g-80s are optionally available as a set. 4. these are products from ando electric. for details, consult ando electric. in-circuit emulator ie-17k ie-17k-et note 1 emu-17k note 2 m pd17p207 29 order code m s5a10as17k m s5a13as17k m s7b10as17k m s7b13as17k m s5a10as17201 m s5a10as17207 m s5a13as17201 m s5a13as17207 m s7b10as17201 m s7b10as17207 m s7b13as17201 m s7b13as17207 m s5a10ie17k m s5a13ie17k m s7b10ie17k m s7b13ie17k software outline as17k is an assembler that can be used in common with the 17k series products. when developing the program of the m pd17p207, as17k is used in combination with a device file (as17201 or as17207). as17201 is a device file for m pd17201a. as17207 is a device file for m pd17207. these are used in combination with an assembler for the 17k series (as17k). simplehost is a software package that enables man- machine interface on the windows tm when a program is developed by using an in-circuit emulator and a personal computer. name 17k series assembler (as17k) device file as17201 as17207 support software ( simple- host ) supply 5" 2hd 3.5" 2hd 5" 2hc 3.5" 2hc 5" 2hd 3.5" 2hd 5" 2hc 3.5" 2hc 5" 2hd 3.5" 2hd 5" 2hc 3.5" 2hc os media ms-dos tm pc dos tm ms-dos pc dos ms-dos windows pc dos host machine pc-9800 series ibm pc/at pc-9800 series ibm pc/at pc-9800 series ibm pc/at remark the corresponding os versions are as follows: os version ms-dos ver. 3.30 to ver. 5.00a note pc dos ver. 3.1 to ver. 5.0 note windows ver. 3.0 to ver. 3.1 note ver. 5.00/5.00a of ms-dos and ver. 5.0 of pc dos have a task swap function, but this function cannot be used with this software. m pd17p207 30 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconduc- tor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. m pd17p207 31 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8 [memo] the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. simplehost is a trademark of nec corporation. ms-dos and windows are trademarks of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 m pd17p207 |
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